SoC Architecture Overview

Overview

RVComp is a System-on-Chip (SoC) that implements the RISC-V ISA (RV32IMAZicsr_Zifencei). This SoC is a fully functional system integrating a CPU, Memory Management Unit (MMU), cache hierarchy, peripherals, and a DRAM controller.

Architecture Diagram

        %%{init: {'flowchart': {'curve': 'stepAfter'}}}%%
flowchart TD
    CPU["RVCpu (RV32IMA_Zicsr_Zicntr_Zifencei)"] --> MMU["MMU (Sv32) <br> (has ITLB/DTLB/PTW/L1 I/D Cache)"]
    MMU --> L2["L2 Cache <br> (Large unified cache)"]
    L2 --> AXI["AXI Based Interconnect (Address Decode)"]
    AXI --- Bus[" "]
    style Bus width:0px,height:0px,fill:none,stroke:none
    Bus --> bootrom
    Bus --> CLINT
    Bus --> PLIC
    Bus --> UART
    Bus --> DRAM[DRAM Controller]
    Bus --> ETH["Ethernet MAC"]
    Bus --> SDCRAM["sdcram"]

Module Hierarchy

soc (soc/soc.v)
├── axi_interconnect (soc/axi_interconnect.v)  # AXI bus interconnect
│
├── clint (clint/clint.v)                      # Core-local interrupt controller
│
├── cpu (cpu/cpu.v)
│   ├── alu (cpu/alu.v)                        # Arithmetic Logic Unit
│   ├── bimodal (cpu/bimodal.v)                # Branch predictor
│   ├── bru (cpu/bru.v)                        # Branch resolution unit
│   ├── csr_regfile (cpu/csr_regfile.v)        # CSR register file
│   ├── csralu (cpu/csralu.v)                  # CSR operation ALU
│   ├── decoder (cpu/decoder.v)                # Instruction decoder
│   ├── divider (cpu/divider.v)                # Divider
│   ├── ifu (cpu/ifu.v)                        # Instruction fetch unit
│   ├── imm_gen (cpu/imm_gen.v)                # Immediate generator
│   ├── lsu (cpu/lsu.v)                        # Load/store unit
│   │   ├── amo_decoder (cpu/amo_decoder.v)    # Atomic instruction decoder
│   │   └── amoalu (cpu/amoalu.v)              # Atomic operation ALU
│   ├── multiplier (cpu/multiplier.v)          # Multiplier
│   └── regfile (cpu/regfile.v)                # General-purpose register file
│
├── dram_controller (dram/dram_controller.v)   # DRAM controller
│   ├── async_fifo (async_fifo.v)              # Asynchronous FIFO
│   └── synchronizer (synchronizer.v) ×3       # Clock domain synchronization
│   └── mig_7series_0 (Xilinx IP)              # MIG DDR2/DDR3 controller
│
├── l2_cache (cache/l2_cache.v)                # L2 unified cache
│
├── mmu (mmu/mmu.v)
│   ├── dtlb (mmu/dtlb.v)                      # Data TLB
│   ├── itlb (mmu/itlb.v)                      # Instruction TLB
│   ├── l1_dcache (cache/l1_dcache.v)          # L1 data cache
│   ├── l1_icache (cache/l1_icache.v)          # L1 instruction cache
│   └── ptw (mmu/ptw.v)                        # Page table walker
│
├── plic (plic/plic.v)                         # Platform-level interrupt controller
│
├── uart (uart/uart.v)                         # UART controller
│   ├── fifo (uart/fifo.v)                     # FIFO buffer
│   ├── uart_rx (uart/uart_rx.v)               # UART receiver
│   └── uart_tx (uart/uart_tx.v)               # UART transmitter
│
├── ether_rmii (ether/ether_rmii.v)            # Ethernet MAC, Nexys 4 DDR (RMII)
├── ether_mii (ether/ether_mii.v)              # Ethernet MAC, Arty A7 (MII)
│
└── sdcram_controller (sdcram/sdcram_controller.v)  # RAM-like storage access wrapper
    └── sdcram (sdcram/sdcram.v)               # Cache and storage access core

Component Details

1. CPU

A 5-stage pipeline RISC-V CPU core. Supports the RV32IMA instruction set and implements Machine/Supervisor/User privilege modes. Branch performance is enhanced by a branch predictor (Bimodal + BTB).

2. MMU

SV32 virtual memory management unit. Implements fast address translation via ITLB/DTLB and TLB miss handling through a hardware page table walker (PTW).

3. L2 Cache

A 4-way set-associative unified cache. Caches both instructions and data, managed with a PLRU replacement algorithm. Uses PIPT (Physically Indexed, Physically Tagged) addressing.

4. AXI Interconnect

AXI4-compliant bus interconnect. Arbitrates memory and I/O accesses from the CPU and routes them to appropriate peripherals.

5. Peripherals

CLINT

Core-Local Interrupt Controller. Features a 64-bit timer (mtime) and timer compare register (mtimecmp), generating timer interrupts and software interrupts (IPI).

PLIC

Platform-Level Interrupt Controller. Arbitrates external interrupts based on priority and delivers interrupts to M-mode and S-mode contexts.

UART

RS-232 serial communication controller. Equipped with transmit/receive FIFOs and configurable baud rate. Used for system debugging and program loading during boot.

bootrom

8KB bootrom. Stores initialization code and bootloader executed after reset. Supports program loading via UART or MMC.

DRAM Controller

DDR2/DDR3 controller using Xilinx MIG (Memory Interface Generator). Converts AXI protocol to DRAM commands and manages main memory access.

Ethernet MAC

10/100 Mbps Ethernet controller. Supports RMII on Nexys 4 DDR and MII on Arty A7. Hardware performs MAC address filtering and FCS computation/verification. The RX and TX buffer sizes are selected at synthesis time.

sdcram

A wrapper that makes storage accessible like RAM via a sliding MMIO window, backed by an on-chip cache. Available on Nexys 4 DDR. Linux software refers to this storage path as mmc by convention.

Configuration Files

Project configuration is managed through the following files:

Hardware Configuration

  • config.vh (src/config.vh)

    • Cache sizes (L0/L1/L2)

    • TLB entry counts (ITLB/DTLB)

    • Branch predictor depth

    • Updated by the configuration utilities (make menuconfig, make cliconfig, or uv run --project tools/ setting)

System Constants

  • rvcom.vh (src/rvcom.vh)

    • Memory map definitions

    • CSR address definitions

    • Exception code definitions

    • Interrupt definitions

    • Bus width definitions

Bus Protocol

  • axi.vh (src/axi.vh)

    • AXI4 protocol definitions

    • AWADDR, WDATA, BRESP, RRESP

    • AWPROT, ARSIZE, etc.