# SoC Architecture Overview

## Overview

RVCom is a System-on-Chip (SoC) that implements the RISC-V ISA (RV32IMAZicsr_Zifencei). This SoC is a fully functional system integrating a CPU, Memory Management Unit (MMU), cache hierarchy, peripherals, and a DRAM controller.

## System Configuration

<!-- ### SoC Block Diagram　TODO: Figure? -->



### Module Hierarchy

```
soc (soc/soc.v)
├── axi_interconnect (soc/axi_interconnect.v)  # AXI bus interconnect
│
├── clint (clint/clint.v)                      # Core-local interrupt controller
│
├── cpu (cpu/cpu.v)
│   ├── alu (cpu/alu.v)                        # Arithmetic Logic Unit
│   ├── bimodal (cpu/bimodal.v)                # Branch predictor
│   ├── bru (cpu/bru.v)                        # Branch resolution unit
│   ├── csr_regfile (cpu/csr_regfile.v)        # CSR register file
│   ├── csralu (cpu/csralu.v)                  # CSR operation ALU
│   ├── decoder (cpu/decoder.v)                # Instruction decoder
│   ├── divider (cpu/divider.v)                # Divider
│   ├── ifu (cpu/ifu.v)                        # Instruction fetch unit
│   ├── imm_gen (cpu/imm_gen.v)                # Immediate generator
│   ├── lsu (cpu/lsu.v)                        # Load/store unit
│   │   ├── amo_decoder (cpu/amo_decoder.v)    # Atomic instruction decoder
│   │   └── amoalu (cpu/amoalu.v)              # Atomic operation ALU
│   ├── multiplier (cpu/multiplier.v)          # Multiplier
│   └── regfile (cpu/regfile.v)                # General-purpose register file
│
├── dram_controller (dram/dram_controller.v)   # DRAM controller
│   ├── async_fifo (dram/async_fifo.v)         # Asynchronous FIFO
│   └── synchronizer (synchronizer.v) ×3       # Clock domain synchronization
│   └── mig_7series_0 (Xilinx IP)              # MIG DDR2/DDR3 controller
│
├── l2_cache (cache/l2_cache.v)                # L2 unified cache
│
├── mmu (mmu/mmu.v)
│   ├── dtlb (mmu/dtlb.v)                      # Data TLB
│   ├── itlb (mmu/itlb.v)                      # Instruction TLB
│   ├── l1_dcache (cache/l1_dcache.v)          # L1 data cache
│   ├── l1_icache (cache/l1_icache.v)          # L1 instruction cache
│   └── ptw (mmu/ptw.v)                        # Page table walker
│
├── plic (plic/plic.v)                         # Platform-level interrupt controller
│
└── uart (uart/uart.v)                         # UART controller
    ├── fifo (uart/fifo.v)                     # FIFO buffer
    ├── uart_rx (uart/uart_rx.v)               # UART receiver
    └── uart_tx (uart/uart_tx.v)               # UART transmitter
```

### Component Details

#### 1. [CPU](rvcpu.md)
A 5-stage pipeline RISC-V CPU core. Supports the RV32IMA instruction set and implements Machine/Supervisor/User privilege modes. Branch performance is enhanced by a branch predictor (Bimodal + BTB).

#### 2. [MMU](mmu.md)
SV32 virtual memory management unit. Implements fast address translation via ITLB/DTLB and TLB miss handling through a hardware page table walker (PTW).

#### 3. [L2 Cache](l2.md)
A 4-way set-associative unified cache. Caches both instructions and data, managed with a PLRU replacement algorithm. Uses PIPT (Physically Indexed, Physically Tagged) addressing.

#### 4. [AXI Interconnect](interconnect.md)
AXI4-compliant bus interconnect. Arbitrates memory and I/O accesses from the CPU and routes them to appropriate peripherals.

#### 5. Peripherals

##### [CLINT](clint.md)
Core-Local Interrupt Controller. Features a 64-bit timer (mtime) and timer compare register (mtimecmp), generating timer interrupts and software interrupts (IPI).

##### [PLIC](plic.md)
Platform-Level Interrupt Controller. Arbitrates external interrupts based on priority and delivers interrupts to M-mode and S-mode contexts.

##### [UART](uart.md)
RS-232 serial communication controller. Equipped with transmit/receive FIFOs and configurable baud rate. Used for system debugging and program loading during boot.

##### [Boot ROM](bootrom.md)
8KB boot ROM. Stores initialization code and bootloader executed after reset. Supports program loading via UART or execution from DRAM.

##### [DRAM Controller](dram.md)
DDR2/DDR3 controller using Xilinx MIG (Memory Interface Generator). Converts AXI protocol to DRAM commands and manages main memory access.

## Configuration Files

Project configuration is managed through the following files:

### Hardware Configuration
- **config.vh** (src/config.vh)
  - Cache sizes (L0/L1/L2)
  - TLB entry counts (ITLB/DTLB)
  - Branch predictor depth
  - Auto-generated by setting.py

### System Constants
- **rvcom.vh** (src/rvcom.vh)
  - Memory map definitions
  - CSR address definitions
  - Exception code definitions
  - Interrupt definitions
  - Bus width definitions

### Bus Protocol
- **axi.vh** (src/axi.vh)
  - AXI4 protocol definitions
  - AWADDR, WDATA, BRESP, RRESP
  - AWPROT, ARSIZE, etc.

## Related Documentation

- [CPU Architecture](rvcpu.md)
- [MMU Design](mmu.md)
- [L2 Cache](l2.md)
- [AXI Interconnect](interconnect.md)
- [UART Controller](uart.md)
- [DRAM Controller](dram.md)
- [CLINT](clint.md)
- [PLIC](plic.md)
- [Boot ROM](bootrom.md)